Instructions¶

Instructions are encoded by opcodes. Each opcode is represented by a single byte, and is followed by the instruction’s immediate arguments, where present. The only exception are structured control instructions, which consist of several opcodes bracketing their nested instruction sequences.

Note

Gaps in the byte code ranges for encoding instructions are reserved for future extensions.

Control Instructions¶

Control instructions have varying encodings. For structured instructions, the instruction sequences forming nested blocks are terminated with explicit opcodes for $end$ and $else$ .

Block types are encoded in special compressed form, by either the byte $0 x 40$ indicating the empty type, as a single value type, or as a type index encoded as a positive signed integer.

\begin{array}{r} \begin{array}{llcllll} blocktype & ::= & 0 x 40 & \Rightarrow & ϵ \\ | & t : valtype & \Rightarrow & t \\ | & x : s 33 & \Rightarrow & x & (if x \geq 0) \\ instr & ::= & 0 x 00 & \Rightarrow & unreachable \\ | & 0 x 01 & \Rightarrow & nop \\ | & 0 x 02 bt : blocktype (in : instr)^{*} 0 x 0 B & \Rightarrow & block bt {in}^{*} end \\ | & 0 x 03 bt : blocktype (in : instr)^{*} 0 x 0 B & \Rightarrow & loop bt {in}^{*} end \\ | & 0 x 04 bt : blocktype (in : instr)^{*} 0 x 0 B & \Rightarrow & if bt {in}^{*} else ϵ end \\ | & 0 x 04 bt : blocktype ({in}_{1} : instr)^{*} 0 x 05 ({in}_{2} : instr)^{*} 0 x 0 B & \Rightarrow & if bt {in}_{1}^{*} else {in}_{2}^{*} end \\ | & 0 x 0 C l : labelidx & \Rightarrow & br l \\ | & 0 x 0 D l : labelidx & \Rightarrow & br_if l \\ | & 0 x 0 E l^{*} : vec (labelidx) l_{N} : labelidx & \Rightarrow & br_table l^{*} l_{N} \\ | & 0 x 0 F & \Rightarrow & return \\ | & 0 x 10 x : funcidx & \Rightarrow & call x \\ | & 0 x 11 y : typeidx x : tableidx & \Rightarrow & call_indirect x y \end{array} \end{array}

Note

The $else$ opcode $0 x 05$ in the encoding of an $if$ instruction can be omitted if the following instruction sequence is empty.

Unlike any other occurrence, the type index in a block type is encoded as a positive signed integer, so that its signed LEB128 bit pattern cannot collide with the encoding of value types or the special code $0 x 40$ , which correspond to the LEB128 encoding of negative integers. To avoid any loss in the range of allowed indices, it is treated as a 33 bit signed integer.

Reference Instructions¶

Reference instructions are represented by single byte codes.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xD 0 t : reftype & \Rightarrow & ref . null t \\ | & 0 xD 1 & \Rightarrow & ref . is_null \\ | & 0 xD 2 x : funcidx & \Rightarrow & ref . func x \end{array} \end{array}

Parametric Instructions¶

Parametric instructions are represented by single byte codes, possibly followed by a type annotation.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 x 1 A & \Rightarrow & drop \\ | & 0 x 1 B & \Rightarrow & select \\ | & 0 x 1 C t^{*} : vec (valtype) & \Rightarrow & select t^{*} \end{array} \end{array}

Variable Instructions¶

Variable instructions are represented by byte codes followed by the encoding of the respective index.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 x 20 x : localidx & \Rightarrow & local . get x \\ | & 0 x 21 x : localidx & \Rightarrow & local . set x \\ | & 0 x 22 x : localidx & \Rightarrow & local . tee x \\ | & 0 x 23 x : globalidx & \Rightarrow & global . get x \\ | & 0 x 24 x : globalidx & \Rightarrow & global . set x \end{array} \end{array}

Table Instructions¶

Table instructions are represented either by a single byte or a one byte prefix followed by a variable-length unsigned integer.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 x 25 x : tableidx & \Rightarrow & table . get x \\ | & 0 x 26 x : tableidx & \Rightarrow & table . set x \\ | & 0 xFC 12 : u 32 y : elemidx x : tableidx & \Rightarrow & table . init x y \\ | & 0 xFC 13 : u 32 x : elemidx & \Rightarrow & elem . drop x \\ | & 0 xFC 14 : u 32 x : tableidx y : tableidx & \Rightarrow & table . copy x y \\ | & 0 xFC 15 : u 32 x : tableidx & \Rightarrow & table . grow x \\ | & 0 xFC 16 : u 32 x : tableidx & \Rightarrow & table . size x \\ | & 0 xFC 17 : u 32 x : tableidx & \Rightarrow & table . fill x \end{array} \end{array}

Memory Instructions¶

Each variant of memory instruction is encoded with a different byte code. Loads and stores are followed by the encoding of their $memarg$ immediate.

\begin{array}{r} \begin{array}{llclll} memarg & ::= & a : u 32 o : u 32 & \Rightarrow & {align a, offset o} \\ instr & ::= & \dots \\ | & 0 x 28 m : memarg & \Rightarrow & i 32 . load m \\ | & 0 x 29 m : memarg & \Rightarrow & i 64 . load m \\ | & 0 x 2 A m : memarg & \Rightarrow & f 32 . load m \\ | & 0 x 2 B m : memarg & \Rightarrow & f 64 . load m \\ | & 0 x 2 C m : memarg & \Rightarrow & i 32 . load 8_s m \\ | & 0 x 2 D m : memarg & \Rightarrow & i 32 . load 8_u m \\ | & 0 x 2 E m : memarg & \Rightarrow & i 32 . load 16_s m \\ | & 0 x 2 F m : memarg & \Rightarrow & i 32 . load 16_u m \\ | & 0 x 30 m : memarg & \Rightarrow & i 64 . load 8_s m \\ | & 0 x 31 m : memarg & \Rightarrow & i 64 . load 8_u m \\ | & 0 x 32 m : memarg & \Rightarrow & i 64 . load 16_s m \\ | & 0 x 33 m : memarg & \Rightarrow & i 64 . load 16_u m \\ | & 0 x 34 m : memarg & \Rightarrow & i 64 . load 32_s m \\ | & 0 x 35 m : memarg & \Rightarrow & i 64 . load 32_u m \\ | & 0 x 36 m : memarg & \Rightarrow & i 32 . store m \\ | & 0 x 37 m : memarg & \Rightarrow & i 64 . store m \\ | & 0 x 38 m : memarg & \Rightarrow & f 32 . store m \\ | & 0 x 39 m : memarg & \Rightarrow & f 64 . store m \\ | & 0 x 3 A m : memarg & \Rightarrow & i 32 . store 8 m \\ | & 0 x 3 B m : memarg & \Rightarrow & i 32 . store 16 m \\ | & 0 x 3 C m : memarg & \Rightarrow & i 64 . store 8 m \\ | & 0 x 3 D m : memarg & \Rightarrow & i 64 . store 16 m \\ | & 0 x 3 E m : memarg & \Rightarrow & i 64 . store 32 m \\ | & 0 x 3 F 0 x 00 & \Rightarrow & memory . size \\ | & 0 x 40 0 x 00 & \Rightarrow & memory . grow \\ | & 0 xFC 8 : u 32 x : dataidx 0 x 00 & \Rightarrow & memory . init x \\ | & 0 xFC 9 : u 32 x : dataidx & \Rightarrow & data . drop x \\ | & 0 xFC 10 : u 32 0 x 00 0 x 00 & \Rightarrow & memory . copy \\ | & 0 xFC 11 : u 32 0 x 00 & \Rightarrow & memory . fill \end{array} \end{array}

Note

In future versions of WebAssembly, the additional zero bytes occurring in the encoding of the $memory . size$ , $memory . grow$ , $memory . copy$ , and $memory . fill$ instructions may be used to index additional memories.

Atomic Memory Instructions¶

Each variant of atomic memory instruction is encoded with a different byte code. Loads, stores and RMW instructions are followed by the encoding of their $memarg$ immediate.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFE 00 : u 32 m : memarg & \Rightarrow & memory . atomic . notify m \\ | & 0 xFE 01 : u 32 m : memarg & \Rightarrow & memory . atomic . wait 32 m \\ | & 0 xFE 02 : u 32 m : memarg & \Rightarrow & memory . atomic . wait 64 m \\ | & 0 xFE 03 : u 32 0 x 00 & \Rightarrow & atomic . fence \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 16 : u 32 m : memarg & \Rightarrow & i 32 . atomic . load m \\ | & 0 xFE 17 : u 32 m : memarg & \Rightarrow & i 64 . atomic . load m \\ | & 0 xFE 18 : u 32 m : memarg & \Rightarrow & i 32 . atomic . load 8_u m \\ | & 0 xFE 19 : u 32 m : memarg & \Rightarrow & i 32 . atomic . load 16_u m \\ | & 0 xFE 20 : u 32 m : memarg & \Rightarrow & i 64 . atomic . load 8_u m \\ | & 0 xFE 21 : u 32 m : memarg & \Rightarrow & i 64 . atomic . load 16_u m \\ | & 0 xFE 22 : u 32 m : memarg & \Rightarrow & i 64 . atomic . load 32_u m \\ | & 0 xFE 23 : u 32 m : memarg & \Rightarrow & i 32 . atomic . store m \\ | & 0 xFE 24 : u 32 m : memarg & \Rightarrow & i 64 . atomic . store m \\ | & 0 xFE 25 : u 32 m : memarg & \Rightarrow & i 32 . atomic . store 8 m \\ | & 0 xFE 26 : u 32 m : memarg & \Rightarrow & i 32 . atomic . store 16 m \\ | & 0 xFE 27 : u 32 m : memarg & \Rightarrow & i 64 . atomic . store 8 m \\ | & 0 xFE 28 : u 32 m : memarg & \Rightarrow & i 64 . atomic . store 16 m \\ | & 0 xFE 29 : u 32 m : memarg & \Rightarrow & i 64 . atomic . store 32 m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 30 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . add m \\ | & 0 xFE 31 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . add m \\ | & 0 xFE 32 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . add_u m \\ | & 0 xFE 33 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . add_u m \\ | & 0 xFE 34 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . add_u m \\ | & 0 xFE 35 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . add_u m \\ | & 0 xFE 36 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . add_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 37 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . sub m \\ | & 0 xFE 38 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . sub m \\ | & 0 xFE 39 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . sub_u m \\ | & 0 xFE 40 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . sub_u m \\ | & 0 xFE 41 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . sub_u m \\ | & 0 xFE 42 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . sub_u m \\ | & 0 xFE 43 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . sub_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 44 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . and m \\ | & 0 xFE 45 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . and m \\ | & 0 xFE 46 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . and_u m \\ | & 0 xFE 47 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . and_u m \\ | & 0 xFE 48 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . and_u m \\ | & 0 xFE 49 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . and_u m \\ | & 0 xFE 50 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . and_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 51 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . or m \\ | & 0 xFE 52 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . or m \\ | & 0 xFE 53 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . or_u m \\ | & 0 xFE 54 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . or_u m \\ | & 0 xFE 55 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . or_u m \\ | & 0 xFE 56 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . or_u m \\ | & 0 xFE 57 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . or_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 58 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . xor m \\ | & 0 xFE 59 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . xor m \\ | & 0 xFE 60 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . xor_u m \\ | & 0 xFE 61 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . xor_u m \\ | & 0 xFE 62 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . xor_u m \\ | & 0 xFE 63 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . xor_u m \\ | & 0 xFE 64 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . xor_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 65 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . xchg m \\ | & 0 xFE 66 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . xchg m \\ | & 0 xFE 67 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . xchg_u m \\ | & 0 xFE 68 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . xchg_u m \\ | & 0 xFE 69 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . xchg_u m \\ | & 0 xFE 70 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . xchg_u m \\ | & 0 xFE 71 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . xchg_u m \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFE 72 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw . cmpxchg m \\ | & 0 xFE 73 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw . cmpxchg m \\ | & 0 xFE 74 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 8 . cmpxchg_u m \\ | & 0 xFE 75 : u 32 m : memarg & \Rightarrow & i 32 . atomic . rmw 16 . cmpxchg_u m \\ | & 0 xFE 76 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 8 . cmpxchg_u m \\ | & 0 xFE 77 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 16 . cmpxchg_u m \\ | & 0 xFE 78 : u 32 m : memarg & \Rightarrow & i 64 . atomic . rmw 32 . cmpxchg_u m \end{array} \end{array}

Numeric Instructions¶

All variants of numeric instructions are represented by separate byte codes.

The $const$ instructions are followed by the respective literal.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 x 41 n : i 32 & \Rightarrow & i 32 . const n \\ | & 0 x 42 n : i 64 & \Rightarrow & i 64 . const n \\ | & 0 x 43 z : f 32 & \Rightarrow & f 32 . const z \\ | & 0 x 44 z : f 64 & \Rightarrow & f 64 . const z \end{array} \end{array}

All other numeric instructions are plain opcodes without any immediates.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 x 45 & \Rightarrow & i 32 . eqz \\ | & 0 x 46 & \Rightarrow & i 32 . eq \\ | & 0 x 47 & \Rightarrow & i 32 . ne \\ | & 0 x 48 & \Rightarrow & i 32 . lt_s \\ | & 0 x 49 & \Rightarrow & i 32 . lt_u \\ | & 0 x 4 A & \Rightarrow & i 32 . gt_s \\ | & 0 x 4 B & \Rightarrow & i 32 . gt_u \\ | & 0 x 4 C & \Rightarrow & i 32 . le_s \\ | & 0 x 4 D & \Rightarrow & i 32 . le_u \\ | & 0 x 4 E & \Rightarrow & i 32 . ge_s \\ | & 0 x 4 F & \Rightarrow & i 32 . ge_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 50 & \Rightarrow & i 64 . eqz \\ | & 0 x 51 & \Rightarrow & i 64 . eq \\ | & 0 x 52 & \Rightarrow & i 64 . ne \\ | & 0 x 53 & \Rightarrow & i 64 . lt_s \\ | & 0 x 54 & \Rightarrow & i 64 . lt_u \\ | & 0 x 55 & \Rightarrow & i 64 . gt_s \\ | & 0 x 56 & \Rightarrow & i 64 . gt_u \\ | & 0 x 57 & \Rightarrow & i 64 . le_s \\ | & 0 x 58 & \Rightarrow & i 64 . le_u \\ | & 0 x 59 & \Rightarrow & i 64 . ge_s \\ | & 0 x 5 A & \Rightarrow & i 64 . ge_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 5 B & \Rightarrow & f 32 . eq \\ | & 0 x 5 C & \Rightarrow & f 32 . ne \\ | & 0 x 5 D & \Rightarrow & f 32 . lt \\ | & 0 x 5 E & \Rightarrow & f 32 . gt \\ | & 0 x 5 F & \Rightarrow & f 32 . le \\ | & 0 x 60 & \Rightarrow & f 32 . ge \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 61 & \Rightarrow & f 64 . eq \\ | & 0 x 62 & \Rightarrow & f 64 . ne \\ | & 0 x 63 & \Rightarrow & f 64 . lt \\ | & 0 x 64 & \Rightarrow & f 64 . gt \\ | & 0 x 65 & \Rightarrow & f 64 . le \\ | & 0 x 66 & \Rightarrow & f 64 . ge \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 67 & \Rightarrow & i 32 . clz \\ | & 0 x 68 & \Rightarrow & i 32 . ctz \\ | & 0 x 69 & \Rightarrow & i 32 . popcnt \\ | & 0 x 6 A & \Rightarrow & i 32 . add \\ | & 0 x 6 B & \Rightarrow & i 32 . sub \\ | & 0 x 6 C & \Rightarrow & i 32 . mul \\ | & 0 x 6 D & \Rightarrow & i 32 . div_s \\ | & 0 x 6 E & \Rightarrow & i 32 . div_u \\ | & 0 x 6 F & \Rightarrow & i 32 . rem_s \\ | & 0 x 70 & \Rightarrow & i 32 . rem_u \\ | & 0 x 71 & \Rightarrow & i 32 . and \\ | & 0 x 72 & \Rightarrow & i 32 . or \\ | & 0 x 73 & \Rightarrow & i 32 . xor \\ | & 0 x 74 & \Rightarrow & i 32 . shl \\ | & 0 x 75 & \Rightarrow & i 32 . shr_s \\ | & 0 x 76 & \Rightarrow & i 32 . shr_u \\ | & 0 x 77 & \Rightarrow & i 32 . rotl \\ | & 0 x 78 & \Rightarrow & i 32 . rotr \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 79 & \Rightarrow & i 64 . clz \\ | & 0 x 7 A & \Rightarrow & i 64 . ctz \\ | & 0 x 7 B & \Rightarrow & i 64 . popcnt \\ | & 0 x 7 C & \Rightarrow & i 64 . add \\ | & 0 x 7 D & \Rightarrow & i 64 . sub \\ | & 0 x 7 E & \Rightarrow & i 64 . mul \\ | & 0 x 7 F & \Rightarrow & i 64 . div_s \\ | & 0 x 80 & \Rightarrow & i 64 . div_u \\ | & 0 x 81 & \Rightarrow & i 64 . rem_s \\ | & 0 x 82 & \Rightarrow & i 64 . rem_u \\ | & 0 x 83 & \Rightarrow & i 64 . and \\ | & 0 x 84 & \Rightarrow & i 64 . or \\ | & 0 x 85 & \Rightarrow & i 64 . xor \\ | & 0 x 86 & \Rightarrow & i 64 . shl \\ | & 0 x 87 & \Rightarrow & i 64 . shr_s \\ | & 0 x 88 & \Rightarrow & i 64 . shr_u \\ | & 0 x 89 & \Rightarrow & i 64 . rotl \\ | & 0 x 8 A & \Rightarrow & i 64 . rotr \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 8 B & \Rightarrow & f 32 . abs \\ | & 0 x 8 C & \Rightarrow & f 32 . neg \\ | & 0 x 8 D & \Rightarrow & f 32 . ceil \\ | & 0 x 8 E & \Rightarrow & f 32 . floor \\ | & 0 x 8 F & \Rightarrow & f 32 . trunc \\ | & 0 x 90 & \Rightarrow & f 32 . nearest \\ | & 0 x 91 & \Rightarrow & f 32 . sqrt \\ | & 0 x 92 & \Rightarrow & f 32 . add \\ | & 0 x 93 & \Rightarrow & f 32 . sub \\ | & 0 x 94 & \Rightarrow & f 32 . mul \\ | & 0 x 95 & \Rightarrow & f 32 . div \\ | & 0 x 96 & \Rightarrow & f 32 . \min \\ | & 0 x 97 & \Rightarrow & f 32 . \max \\ | & 0 x 98 & \Rightarrow & f 32 . copysign \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 x 99 & \Rightarrow & f 64 . abs \\ | & 0 x 9 A & \Rightarrow & f 64 . neg \\ | & 0 x 9 B & \Rightarrow & f 64 . ceil \\ | & 0 x 9 C & \Rightarrow & f 64 . floor \\ | & 0 x 9 D & \Rightarrow & f 64 . trunc \\ | & 0 x 9 E & \Rightarrow & f 64 . nearest \\ | & 0 x 9 F & \Rightarrow & f 64 . sqrt \\ | & 0 xA 0 & \Rightarrow & f 64 . add \\ | & 0 xA 1 & \Rightarrow & f 64 . sub \\ | & 0 xA 2 & \Rightarrow & f 64 . mul \\ | & 0 xA 3 & \Rightarrow & f 64 . div \\ | & 0 xA 4 & \Rightarrow & f 64 . \min \\ | & 0 xA 5 & \Rightarrow & f 64 . \max \\ | & 0 xA 6 & \Rightarrow & f 64 . copysign \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xA 7 & \Rightarrow & i 32 . wrap_i 64 \\ | & 0 xA 8 & \Rightarrow & i 32 . trunc_f 32_s \\ | & 0 xA 9 & \Rightarrow & i 32 . trunc_f 32_u \\ | & 0 xAA & \Rightarrow & i 32 . trunc_f 64_s \\ | & 0 xAB & \Rightarrow & i 32 . trunc_f 64_u \\ | & 0 xAC & \Rightarrow & i 64 . extend_i 32_s \\ | & 0 xAD & \Rightarrow & i 64 . extend_i 32_u \\ | & 0 xAE & \Rightarrow & i 64 . trunc_f 32_s \\ | & 0 xAF & \Rightarrow & i 64 . trunc_f 32_u \\ | & 0 xB 0 & \Rightarrow & i 64 . trunc_f 64_s \\ | & 0 xB 1 & \Rightarrow & i 64 . trunc_f 64_u \\ | & 0 xB 2 & \Rightarrow & f 32 . convert_i 32_s \\ | & 0 xB 3 & \Rightarrow & f 32 . convert_i 32_u \\ | & 0 xB 4 & \Rightarrow & f 32 . convert_i 64_s \\ | & 0 xB 5 & \Rightarrow & f 32 . convert_i 64_u \\ | & 0 xB 6 & \Rightarrow & f 32 . demote_f 64 \\ | & 0 xB 7 & \Rightarrow & f 64 . convert_i 32_s \\ | & 0 xB 8 & \Rightarrow & f 64 . convert_i 32_u \\ | & 0 xB 9 & \Rightarrow & f 64 . convert_i 64_s \\ | & 0 xBA & \Rightarrow & f 64 . convert_i 64_u \\ | & 0 xBB & \Rightarrow & f 64 . promote_f 32 \\ | & 0 xBC & \Rightarrow & i 32 . reinterpret_f 32 \\ | & 0 xBD & \Rightarrow & i 64 . reinterpret_f 64 \\ | & 0 xBE & \Rightarrow & f 32 . reinterpret_i 32 \\ | & 0 xBF & \Rightarrow & f 64 . reinterpret_i 64 \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xC 0 & \Rightarrow & i 32 . extend 8_s \\ | & 0 xC 1 & \Rightarrow & i 32 . extend 16_s \\ | & 0 xC 2 & \Rightarrow & i 64 . extend 8_s \\ | & 0 xC 3 & \Rightarrow & i 64 . extend 16_s \\ | & 0 xC 4 & \Rightarrow & i 64 . extend 32_s \end{array} \end{array}

The saturating truncation instructions all have a one byte prefix, whereas the actual opcode is encoded by a variable-length unsigned integer.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFC 0 : u 32 & \Rightarrow & i 32 . trunc_sat_f 32_s \\ | & 0 xFC 1 : u 32 & \Rightarrow & i 32 . trunc_sat_f 32_u \\ | & 0 xFC 2 : u 32 & \Rightarrow & i 32 . trunc_sat_f 64_s \\ | & 0 xFC 3 : u 32 & \Rightarrow & i 32 . trunc_sat_f 64_u \\ | & 0 xFC 4 : u 32 & \Rightarrow & i 64 . trunc_sat_f 32_s \\ | & 0 xFC 5 : u 32 & \Rightarrow & i 64 . trunc_sat_f 32_u \\ | & 0 xFC 6 : u 32 & \Rightarrow & i 64 . trunc_sat_f 64_s \\ | & 0 xFC 7 : u 32 & \Rightarrow & i 64 . trunc_sat_f 64_u \end{array} \end{array}

Vector Instructions¶

All variants of vector instructions are represented by separate byte codes. They all have a one byte prefix, whereas the actual opcode is encoded by a variable-length unsigned integer.

Vector loads and stores are followed by the encoding of their $memarg$ immediate.

\begin{array}{r} \begin{array}{llclll} laneidx & ::= & l : byte & \Rightarrow & l \\ instr & ::= & \dots \\ | & 0 xFD 0 : u 32 m : memarg & \Rightarrow & v 128 . load m \\ | & 0 xFD 1 : u 32 m : memarg & \Rightarrow & v 128 . load 8 x 8_s m \\ | & 0 xFD 2 : u 32 m : memarg & \Rightarrow & v 128 . load 8 x 8_u m \\ | & 0 xFD 3 : u 32 m : memarg & \Rightarrow & v 128 . load 16 x 4_s m \\ | & 0 xFD 4 : u 32 m : memarg & \Rightarrow & v 128 . load 16 x 4_u m \\ | & 0 xFD 5 : u 32 m : memarg & \Rightarrow & v 128 . load 32 x 2_s m \\ | & 0 xFD 6 : u 32 m : memarg & \Rightarrow & v 128 . load 32 x 2_u m \\ | & 0 xFD 7 : u 32 m : memarg & \Rightarrow & v 128 . load 8_splat m \\ | & 0 xFD 8 : u 32 m : memarg & \Rightarrow & v 128 . load 16_splat m \\ | & 0 xFD 9 : u 32 m : memarg & \Rightarrow & v 128 . load 32_splat m \\ | & 0 xFD 10 : u 32 m : memarg & \Rightarrow & v 128 . load 64_splat m \\ | & 0 xFD 92 : u 32 m : memarg & \Rightarrow & v 128 . load 32_zero m \\ | & 0 xFD 93 : u 32 m : memarg & \Rightarrow & v 128 . load 64_zero m \\ | & 0 xFD 11 : u 32 m : memarg & \Rightarrow & v 128 . store m \\ | & 0 xFD 84 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . load 8_lane m l \\ | & 0 xFD 85 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . load 16_lane m l \\ | & 0 xFD 86 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . load 32_lane m l \\ | & 0 xFD 87 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . load 64_lane m l \\ | & 0 xFD 88 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . store 8_lane m l \\ | & 0 xFD 89 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . store 16_lane m l \\ | & 0 xFD 90 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . store 32_lane m l \\ | & 0 xFD 91 : u 32 m : memarg l : laneidx & \Rightarrow & v 128 . store 64_lane m l \end{array} \end{array}

The $const$ instruction is followed by 16 immediate bytes, which are converted into a $i 128$ in $littleendian$ byte order:

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFD 12 : u 32 (b : byte)^{16} & \Rightarrow & v 128 . const {bytes}_{i 128}^{- 1} (b_{0} \dots b_{15}) \end{array} \end{array}

The $shuffle$ instruction is also followed by the encoding of 16 $laneidx$ immediates.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFD 13 : u 32 (l : laneidx)^{16} & \Rightarrow & i 8 x 16 . shuffle l^{16} \end{array} \end{array}

$extract_lane$ and $replace_lane$ instructions are followed by the encoding of a $laneidx$ immediate.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFD 21 : u 32 l : laneidx & \Rightarrow & i 8 x 16 . extract_lane_s l \\ | & 0 xFD 22 : u 32 l : laneidx & \Rightarrow & i 8 x 16 . extract_lane_u l \\ | & 0 xFD 23 : u 32 l : laneidx & \Rightarrow & i 8 x 16 . replace_lane l \\ | & 0 xFD 24 : u 32 l : laneidx & \Rightarrow & i 16 x 8 . extract_lane_s l \\ | & 0 xFD 25 : u 32 l : laneidx & \Rightarrow & i 16 x 8 . extract_lane_u l \\ | & 0 xFD 26 : u 32 l : laneidx & \Rightarrow & i 16 x 8 . replace_lane l \\ | & 0 xFD 27 : u 32 l : laneidx & \Rightarrow & i 32 x 4 . extract_lane l \\ | & 0 xFD 28 : u 32 l : laneidx & \Rightarrow & i 32 x 4 . replace_lane l \\ | & 0 xFD 29 : u 32 l : laneidx & \Rightarrow & i 64 x 2 . extract_lane l \\ | & 0 xFD 30 : u 32 l : laneidx & \Rightarrow & i 64 x 2 . replace_lane l \\ | & 0 xFD 31 : u 32 l : laneidx & \Rightarrow & f 32 x 4 . extract_lane l \\ | & 0 xFD 32 : u 32 l : laneidx & \Rightarrow & f 32 x 4 . replace_lane l \\ | & 0 xFD 33 : u 32 l : laneidx & \Rightarrow & f 64 x 2 . extract_lane l \\ | & 0 xFD 34 : u 32 l : laneidx & \Rightarrow & f 64 x 2 . replace_lane l \end{array} \end{array}

All other vector instructions are plain opcodes without any immediates.

\begin{array}{r} \begin{array}{llclll} instr & ::= & \dots \\ | & 0 xFD 14 : u 32 & \Rightarrow & i 8 x 16 . swizzle \\ | & 0 xFD 15 : u 32 & \Rightarrow & i 8 x 16 . splat \\ | & 0 xFD 16 : u 32 & \Rightarrow & i 16 x 8 . splat \\ | & 0 xFD 17 : u 32 & \Rightarrow & i 32 x 4 . splat \\ | & 0 xFD 18 : u 32 & \Rightarrow & i 64 x 2 . splat \\ | & 0 xFD 19 : u 32 & \Rightarrow & f 32 x 4 . splat \\ | & 0 xFD 20 : u 32 & \Rightarrow & f 64 x 2 . splat \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 35 : u 32 & \Rightarrow & i 8 x 16 . eq \\ | & 0 xFD 36 : u 32 & \Rightarrow & i 8 x 16 . ne \\ | & 0 xFD 37 : u 32 & \Rightarrow & i 8 x 16 . lt_s \\ | & 0 xFD 38 : u 32 & \Rightarrow & i 8 x 16 . lt_u \\ | & 0 xFD 39 : u 32 & \Rightarrow & i 8 x 16 . gt_s \\ | & 0 xFD 40 : u 32 & \Rightarrow & i 8 x 16 . gt_u \\ | & 0 xFD 41 : u 32 & \Rightarrow & i 8 x 16 . le_s \\ | & 0 xFD 42 : u 32 & \Rightarrow & i 8 x 16 . le_u \\ | & 0 xFD 43 : u 32 & \Rightarrow & i 8 x 16 . ge_s \\ | & 0 xFD 44 : u 32 & \Rightarrow & i 8 x 16 . ge_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 45 : u 32 & \Rightarrow & i 16 x 8 . eq \\ | & 0 xFD 46 : u 32 & \Rightarrow & i 16 x 8 . ne \\ | & 0 xFD 47 : u 32 & \Rightarrow & i 16 x 8 . lt_s \\ | & 0 xFD 48 : u 32 & \Rightarrow & i 16 x 8 . lt_u \\ | & 0 xFD 49 : u 32 & \Rightarrow & i 16 x 8 . gt_s \\ | & 0 xFD 50 : u 32 & \Rightarrow & i 16 x 8 . gt_u \\ | & 0 xFD 51 : u 32 & \Rightarrow & i 16 x 8 . le_s \\ | & 0 xFD 52 : u 32 & \Rightarrow & i 16 x 8 . le_u \\ | & 0 xFD 53 : u 32 & \Rightarrow & i 16 x 8 . ge_s \\ | & 0 xFD 54 : u 32 & \Rightarrow & i 16 x 8 . ge_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 55 : u 32 & \Rightarrow & i 32 x 4 . eq \\ | & 0 xFD 56 : u 32 & \Rightarrow & i 32 x 4 . ne \\ | & 0 xFD 57 : u 32 & \Rightarrow & i 32 x 4 . lt_s \\ | & 0 xFD 58 : u 32 & \Rightarrow & i 32 x 4 . lt_u \\ | & 0 xFD 59 : u 32 & \Rightarrow & i 32 x 4 . gt_s \\ | & 0 xFD 60 : u 32 & \Rightarrow & i 32 x 4 . gt_u \\ | & 0 xFD 61 : u 32 & \Rightarrow & i 32 x 4 . le_s \\ | & 0 xFD 62 : u 32 & \Rightarrow & i 32 x 4 . le_u \\ | & 0 xFD 63 : u 32 & \Rightarrow & i 32 x 4 . ge_s \\ | & 0 xFD 64 : u 32 & \Rightarrow & i 32 x 4 . ge_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 214 : u 32 & \Rightarrow & i 64 x 2 . eq \\ | & 0 xFD 215 : u 32 & \Rightarrow & i 64 x 2 . ne \\ | & 0 xFD 216 : u 32 & \Rightarrow & i 64 x 2 . lt_s \\ | & 0 xFD 217 : u 32 & \Rightarrow & i 64 x 2 . gt_s \\ | & 0 xFD 218 : u 32 & \Rightarrow & i 64 x 2 . le_s \\ | & 0 xFD 219 : u 32 & \Rightarrow & i 64 x 2 . ge_s \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 65 : u 32 & \Rightarrow & f 32 x 4 . eq \\ | & 0 xFD 66 : u 32 & \Rightarrow & f 32 x 4 . ne \\ | & 0 xFD 67 : u 32 & \Rightarrow & f 32 x 4 . lt \\ | & 0 xFD 68 : u 32 & \Rightarrow & f 32 x 4 . gt \\ | & 0 xFD 69 : u 32 & \Rightarrow & f 32 x 4 . le \\ | & 0 xFD 70 : u 32 & \Rightarrow & f 32 x 4 . ge \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 71 : u 32 & \Rightarrow & f 64 x 2 . eq \\ | & 0 xFD 72 : u 32 & \Rightarrow & f 64 x 2 . ne \\ | & 0 xFD 73 : u 32 & \Rightarrow & f 64 x 2 . lt \\ | & 0 xFD 74 : u 32 & \Rightarrow & f 64 x 2 . gt \\ | & 0 xFD 75 : u 32 & \Rightarrow & f 64 x 2 . le \\ | & 0 xFD 76 : u 32 & \Rightarrow & f 64 x 2 . ge \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 77 : u 32 & \Rightarrow & v 128 . not \\ | & 0 xFD 78 : u 32 & \Rightarrow & v 128 . and \\ | & 0 xFD 79 : u 32 & \Rightarrow & v 128 . andnot \\ | & 0 xFD 80 : u 32 & \Rightarrow & v 128 . or \\ | & 0 xFD 81 : u 32 & \Rightarrow & v 128 . xor \\ | & 0 xFD 82 : u 32 & \Rightarrow & v 128 . bitselect \\ | & 0 xFD 83 : u 32 & \Rightarrow & v 128 . any_true \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 96 : u 32 & \Rightarrow & i 8 x 16 . abs \\ | & 0 xFD 97 : u 32 & \Rightarrow & i 8 x 16 . neg \\ | & 0 xFD 98 : u 32 & \Rightarrow & i 8 x 16 . popcnt \\ | & 0 xFD 99 : u 32 & \Rightarrow & i 8 x 16 . all_true \\ | & 0 xFD 100 : u 32 & \Rightarrow & i 8 x 16 . bitmask \\ | & 0 xFD 101 : u 32 & \Rightarrow & i 8 x 16 . narrow_i 16 x 8_s \\ | & 0 xFD 102 : u 32 & \Rightarrow & i 8 x 16 . narrow_i 16 x 8_u \\ | & 0 xFD 107 : u 32 & \Rightarrow & i 8 x 16 . shl \\ | & 0 xFD 108 : u 32 & \Rightarrow & i 8 x 16 . shr_s \\ | & 0 xFD 109 : u 32 & \Rightarrow & i 8 x 16 . shr_u \\ | & 0 xFD 110 : u 32 & \Rightarrow & i 8 x 16 . add \\ | & 0 xFD 111 : u 32 & \Rightarrow & i 8 x 16 . add_sat_s \\ | & 0 xFD 112 : u 32 & \Rightarrow & i 8 x 16 . add_sat_u \\ | & 0 xFD 113 : u 32 & \Rightarrow & i 8 x 16 . sub \\ | & 0 xFD 114 : u 32 & \Rightarrow & i 8 x 16 . sub_sat_s \\ | & 0 xFD 115 : u 32 & \Rightarrow & i 8 x 16 . sub_sat_u \\ | & 0 xFD 118 : u 32 & \Rightarrow & i 8 x 16 . \min_s \\ | & 0 xFD 119 : u 32 & \Rightarrow & i 8 x 16 . \min_u \\ | & 0 xFD 120 : u 32 & \Rightarrow & i 8 x 16 . \max_s \\ | & 0 xFD 121 : u 32 & \Rightarrow & i 8 x 16 . \max_u \\ | & 0 xFD 123 : u 32 & \Rightarrow & i 8 x 16 . avgr_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 124 : u 32 & \Rightarrow & i 16 x 8 . extadd_pairwise_i 8 x 16_s \\ | & 0 xFD 125 : u 32 & \Rightarrow & i 16 x 8 . extadd_pairwise_i 8 x 16_u \\ | & 0 xFD 128 : u 32 & \Rightarrow & i 16 x 8 . abs \\ | & 0 xFD 129 : u 32 & \Rightarrow & i 16 x 8 . neg \\ | & 0 xFD 130 : u 32 & \Rightarrow & i 16 x 8 . q 15 mulr_sat_s \\ | & 0 xFD 131 : u 32 & \Rightarrow & i 16 x 8 . all_true \\ | & 0 xFD 132 : u 32 & \Rightarrow & i 16 x 8 . bitmask \\ | & 0 xFD 133 : u 32 & \Rightarrow & i 16 x 8 . narrow_i 32 x 4_s \\ | & 0 xFD 134 : u 32 & \Rightarrow & i 16 x 8 . narrow_i 32 x 4_u \\ | & 0 xFD 135 : u 32 & \Rightarrow & i 16 x 8 . extend_low_i 8 x 16_s \\ | & 0 xFD 136 : u 32 & \Rightarrow & i 16 x 8 . extend_high_i 8 x 16_s \\ | & 0 xFD 137 : u 32 & \Rightarrow & i 16 x 8 . extend_low_i 8 x 16_u \\ | & 0 xFD 138 : u 32 & \Rightarrow & i 16 x 8 . extend_high_i 8 x 16_u \\ | & 0 xFD 139 : u 32 & \Rightarrow & i 16 x 8 . shl \\ | & 0 xFD 140 : u 32 & \Rightarrow & i 16 x 8 . shr_s \\ | & 0 xFD 141 : u 32 & \Rightarrow & i 16 x 8 . shr_u \\ | & 0 xFD 142 : u 32 & \Rightarrow & i 16 x 8 . add \\ | & 0 xFD 143 : u 32 & \Rightarrow & i 16 x 8 . add_sat_s \\ | & 0 xFD 144 : u 32 & \Rightarrow & i 16 x 8 . add_sat_u \\ | & 0 xFD 145 : u 32 & \Rightarrow & i 16 x 8 . sub \\ | & 0 xFD 146 : u 32 & \Rightarrow & i 16 x 8 . sub_sat_s \\ | & 0 xFD 147 : u 32 & \Rightarrow & i 16 x 8 . sub_sat_u \\ | & 0 xFD 149 : u 32 & \Rightarrow & i 16 x 8 . mul \\ | & 0 xFD 150 : u 32 & \Rightarrow & i 16 x 8 . \min_s \\ | & 0 xFD 151 : u 32 & \Rightarrow & i 16 x 8 . \min_u \\ | & 0 xFD 152 : u 32 & \Rightarrow & i 16 x 8 . \max_s \\ | & 0 xFD 153 : u 32 & \Rightarrow & i 16 x 8 . \max_u \\ | & 0 xFD 155 : u 32 & \Rightarrow & i 16 x 8 . avgr_u \\ | & 0 xFD 156 : u 32 & \Rightarrow & i 16 x 8 . extmul_low_i 8 x 16_s \\ | & 0 xFD 157 : u 32 & \Rightarrow & i 16 x 8 . extmul_high_i 8 x 16_s \\ | & 0 xFD 158 : u 32 & \Rightarrow & i 16 x 8 . extmul_low_i 8 x 16_u \\ | & 0 xFD 159 : u 32 & \Rightarrow & i 16 x 8 . extmul_high_i 8 x 16_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 126 : u 32 & \Rightarrow & i 32 x 4 . extadd_pairwise_i 16 x 8_s \\ | & 0 xFD 127 : u 32 & \Rightarrow & i 32 x 4 . extadd_pairwise_i 16 x 8_u \\ | & 0 xFD 160 : u 32 & \Rightarrow & i 32 x 4 . abs \\ | & 0 xFD 161 : u 32 & \Rightarrow & i 32 x 4 . neg \\ | & 0 xFD 163 : u 32 & \Rightarrow & i 32 x 4 . all_true \\ | & 0 xFD 164 : u 32 & \Rightarrow & i 32 x 4 . bitmask \\ | & 0 xFD 167 : u 32 & \Rightarrow & i 32 x 4 . extend_low_i 16 x 8_s \\ | & 0 xFD 168 : u 32 & \Rightarrow & i 32 x 4 . extend_high_i 16 x 8_s \\ | & 0 xFD 169 : u 32 & \Rightarrow & i 32 x 4 . extend_low_i 16 x 8_u \\ | & 0 xFD 170 : u 32 & \Rightarrow & i 32 x 4 . extend_high_i 16 x 8_u \\ | & 0 xFD 171 : u 32 & \Rightarrow & i 32 x 4 . shl \\ | & 0 xFD 172 : u 32 & \Rightarrow & i 32 x 4 . shr_s \\ | & 0 xFD 173 : u 32 & \Rightarrow & i 32 x 4 . shr_u \\ | & 0 xFD 174 : u 32 & \Rightarrow & i 32 x 4 . add \\ | & 0 xFD 177 : u 32 & \Rightarrow & i 32 x 4 . sub \\ | & 0 xFD 181 : u 32 & \Rightarrow & i 32 x 4 . mul \\ | & 0 xFD 182 : u 32 & \Rightarrow & i 32 x 4 . \min_s \\ | & 0 xFD 183 : u 32 & \Rightarrow & i 32 x 4 . \min_u \\ | & 0 xFD 184 : u 32 & \Rightarrow & i 32 x 4 . \max_s \\ | & 0 xFD 185 : u 32 & \Rightarrow & i 32 x 4 . \max_u \\ | & 0 xFD 186 : u 32 & \Rightarrow & i 32 x 4 . dot_i 16 x 8_s \\ | & 0 xFD 188 : u 32 & \Rightarrow & i 32 x 4 . extmul_low_i 16 x 8_s \\ | & 0 xFD 189 : u 32 & \Rightarrow & i 32 x 4 . extmul_high_i 16 x 8_s \\ | & 0 xFD 190 : u 32 & \Rightarrow & i 32 x 4 . extmul_low_i 16 x 8_u \\ | & 0 xFD 191 : u 32 & \Rightarrow & i 32 x 4 . extmul_high_i 16 x 8_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 192 : u 32 & \Rightarrow & i 64 x 2 . abs \\ | & 0 xFD 193 : u 32 & \Rightarrow & i 64 x 2 . neg \\ | & 0 xFD 195 : u 32 & \Rightarrow & i 64 x 2 . all_true \\ | & 0 xFD 196 : u 32 & \Rightarrow & i 64 x 2 . bitmask \\ | & 0 xFD 199 : u 32 & \Rightarrow & i 64 x 2 . extend_low_i 32 x 4_s \\ | & 0 xFD 200 : u 32 & \Rightarrow & i 64 x 2 . extend_high_i 32 x 4_s \\ | & 0 xFD 201 : u 32 & \Rightarrow & i 64 x 2 . extend_low_i 32 x 4_u \\ | & 0 xFD 202 : u 32 & \Rightarrow & i 64 x 2 . extend_high_i 32 x 4_u \\ | & 0 xFD 203 : u 32 & \Rightarrow & i 64 x 2 . shl \\ | & 0 xFD 204 : u 32 & \Rightarrow & i 64 x 2 . shr_s \\ | & 0 xFD 205 : u 32 & \Rightarrow & i 64 x 2 . shr_u \\ | & 0 xFD 206 : u 32 & \Rightarrow & i 64 x 2 . add \\ | & 0 xFD 209 : u 32 & \Rightarrow & i 64 x 2 . sub \\ | & 0 xFD 213 : u 32 & \Rightarrow & i 64 x 2 . mul \\ | & 0 xFD 220 : u 32 & \Rightarrow & i 64 x 2 . extmul_low_i 32 x 4_s \\ | & 0 xFD 221 : u 32 & \Rightarrow & i 64 x 2 . extmul_high_i 32 x 4_s \\ | & 0 xFD 222 : u 32 & \Rightarrow & i 64 x 2 . extmul_low_i 32 x 4_u \\ | & 0 xFD 223 : u 32 & \Rightarrow & i 64 x 2 . extmul_high_i 32 x 4_u \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 103 : u 32 & \Rightarrow & f 32 x 4 . ceil \\ | & 0 xFD 104 : u 32 & \Rightarrow & f 32 x 4 . floor \\ | & 0 xFD 105 : u 32 & \Rightarrow & f 32 x 4 . trunc \\ | & 0 xFD 106 : u 32 & \Rightarrow & f 32 x 4 . nearest \\ | & 0 xFD 224 : u 32 & \Rightarrow & f 32 x 4 . abs \\ | & 0 xFD 225 : u 32 & \Rightarrow & f 32 x 4 . neg \\ | & 0 xFD 227 : u 32 & \Rightarrow & f 32 x 4 . sqrt \\ | & 0 xFD 228 : u 32 & \Rightarrow & f 32 x 4 . add \\ | & 0 xFD 229 : u 32 & \Rightarrow & f 32 x 4 . sub \\ | & 0 xFD 230 : u 32 & \Rightarrow & f 32 x 4 . mul \\ | & 0 xFD 231 : u 32 & \Rightarrow & f 32 x 4 . div \\ | & 0 xFD 232 : u 32 & \Rightarrow & f 32 x 4 . \min \\ | & 0 xFD 233 : u 32 & \Rightarrow & f 32 x 4 . \max \\ | & 0 xFD 234 : u 32 & \Rightarrow & f 32 x 4 . pmin \\ | & 0 xFD 235 : u 32 & \Rightarrow & f 32 x 4 . pmax \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 116 : u 32 & \Rightarrow & f 64 x 2 . ceil \\ | & 0 xFD 117 : u 32 & \Rightarrow & f 64 x 2 . floor \\ | & 0 xFD 122 : u 32 & \Rightarrow & f 64 x 2 . trunc \\ | & 0 xFD 148 : u 32 & \Rightarrow & f 64 x 2 . nearest \\ | & 0 xFD 236 : u 32 & \Rightarrow & f 64 x 2 . abs \\ | & 0 xFD 237 : u 32 & \Rightarrow & f 64 x 2 . neg \\ | & 0 xFD 239 : u 32 & \Rightarrow & f 64 x 2 . sqrt \\ | & 0 xFD 240 : u 32 & \Rightarrow & f 64 x 2 . add \\ | & 0 xFD 241 : u 32 & \Rightarrow & f 64 x 2 . sub \\ | & 0 xFD 242 : u 32 & \Rightarrow & f 64 x 2 . mul \\ | & 0 xFD 243 : u 32 & \Rightarrow & f 64 x 2 . div \\ | & 0 xFD 244 : u 32 & \Rightarrow & f 64 x 2 . \min \\ | & 0 xFD 245 : u 32 & \Rightarrow & f 64 x 2 . \max \\ | & 0 xFD 246 : u 32 & \Rightarrow & f 64 x 2 . pmin \\ | & 0 xFD 247 : u 32 & \Rightarrow & f 64 x 2 . pmax \end{array} \end{array}

\begin{array}{r} \begin{array}{llclll} | & 0 xFD 248 : u 32 & \Rightarrow & i 32 x 4 . trunc_sat_f 32 x 4_s \\ | & 0 xFD 249 : u 32 & \Rightarrow & i 32 x 4 . trunc_sat_f 32 x 4_u \\ | & 0 xFD 250 : u 32 & \Rightarrow & f 32 x 4 . convert_i 32 x 4_s \\ | & 0 xFD 251 : u 32 & \Rightarrow & f 32 x 4 . convert_i 32 x 4_u \\ | & 0 xFD 252 : u 32 & \Rightarrow & i 32 x 4 . trunc_sat_f 64 x 2_s_zero \\ | & 0 xFD 253 : u 32 & \Rightarrow & i 32 x 4 . trunc_sat_f 64 x 2_u_zero \\ | & 0 xFD 254 : u 32 & \Rightarrow & f 64 x 2 . convert_low_i 32 x 4_s \\ | & 0 xFD 255 : u 32 & \Rightarrow & f 64 x 2 . convert_low_i 32 x 4_u \\ | & 0 xFD 94 : u 32 & \Rightarrow & f 32 x 4 . demote_f 64 x 2_zero \\ | & 0 xFD 95 : u 32 & \Rightarrow & f 64 x 2 . promote_low_f 32 x 4 \end{array} \end{array}

Expressions¶

Expressions are encoded by their instruction sequence terminated with an explicit $0 x 0 B$ opcode for $end$ .

\begin{array}{r} \begin{array}{llclll} expr & ::= & (in : instr)^{*} 0 x 0 B & \Rightarrow & {in}^{*} end \end{array} \end{array}